Memory resources are widely used in current computing platforms, whether for servers, desktop or laptop computers, mobile devices, or consumer and business electronics. The increasing amounts of memory in memory subsystems and the increased densities of the memory devices themselves contribute to an increased number of errors in memories. One technique for addressing the increasing memory errors is to employ ECC (error checking and correction). Traditionally a memory controller performs error detection and correction, although there are emerging on-die ECC technologies as well. ECC has become a basic tool for meeting RAS (reliability, accessibility, and serviceability) expectations in modern memory subsystems.
Common memory architectures include x4, x8, or x16 interfaces, where ‘x4’ refers to a device with a 4 bit wide interface, ‘x8’ refers to a device with an 8 bit wide interface, and ‘x16’ refers to a device with a 16 bits wide interface. Implementations of ECC require extra bits or bandwidth to perform the error detection and correction. The design and number of required ECC bits for implementing ECC is dictated mainly by the memory architecture. For example, many traditional ECC implementations support SDDC (single device data correction) or similar implementations. The number of bits for ECC in a DRAM (dynamic random access memory) DIMM (dual inline memory module) is adequate for x4 SDDC where each DRAM device contributes 4 bytes to a cacheline (e.g., a 4-bit wide interface that provides four bits for each cycle of an 8 cycle burst for a total of 4 bytes or 4B). But the number of bits per cacheline affected by a device failure is larger for x8 devices (8B, or 8-bits per cycle for an 8 cycle burst). Consequently, ECC for x8 memory devices traditionally requires lockstep or a comparable mechanism, and has an associated bandwidth and power penalty. Lockstep refers to a partnership between two regions of memory where ECC information is shared for the partnership to spread error correction across the two regions.
However, in certain systems the additional bandwidth and/or power requirements can be impractical. Certain system implementations may suffer significant performance and/or cost penalties in implementing the logic needed for x8 devices. It will be understood that more ECC bits are required for larger interfaces, and there is an associated performance cost associated with using more ECC bits.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.